With the advancement of CMOS VLSI technology in nanometer regime, the process, the supply voltage, and the on-chip temperature (PVT) variations have been significant issues. These variations make a digital CMOS system vulnerable since drivability of each device changes from the intended design, causing read or write upset in an SRAM, synchronization problems in a latch, and adversely affect delays in logic gates. Among these three ‘canonical’ CMOS circuit types which are an SRAM cell, a latch, and an inverter, an SRAM bitcell is a key component in designing a reliable system due to its highest failure rate. In addition, as the demand for ultra-low power applications has been on the rise, many techniques have been proposed, including parallel computation, clock gating, low swing signaling, dynamic voltage and frequency scaling, low swing flops and latches, and sub-threshold operation. Among these techniques, sub-threshold operation has had a high profile since dynamic power can dramatically be reduced in the sub-threshold region. In this region, sequential logic is more vulnerable to noise than combinational logic, so many sub-threshold SRAM cell structures have been proposed since the introduction of the first sub-threshold operating FFT processor.
For example, a single-ended read port was proposed by introducing two additional read transistors. These additional devices decouple its read bitline from the storage node, so the disturbance of the SRAM cell could be eliminated during read operation, which improved the stability of SRAM cell during read operation. In another example, the number of read access transistors was increased to four. The additional devices could increase the number of rows sharing a bitline due to stacking effects. In another case, a floating VDD scheme was proposed. In this work, write operation in the sub-threshold region was feasible due to a floating VDD during write operation since it weakened the feedback in the SRAM cell. In addition, a virtual ground concept driven by a read buffer foot driver was introduced, which helped leakage reduction from bit lines through read access devices. For realization of write operation in the sub-threshold region, a virtual supply scheme was introduced. In yet another example, a decoupled read port was also introduced in order to improve read static noise margin (RSNM), and halo doping was introduced in the access transistors in order to utilize reverse short channel effect, causing the increase of threshold voltage. This technique was for increasing write margin in sub-threshold region. Lastly, dynamic differential cascade voltage switch logic (DCVSL) was introduced for read access. In order to increase write margin, wordline voltage was boosted. Although these proposed bitcells improved RSNM as well as the number of rows sharing a bit line, write margin was not dramatically improved since each bitcell itself has a feedback loop in the structure so that this loop contends with write access devices. In this disclosure, a circuit arrangement is proposed for an SRAM cell, which eliminates charge contention during write operation.
This section provides background information related to the present disclosure which is not necessarily prior art.